FIR filtering and AES encryption with OpenCL 2.0

40Gbit AES Encryption Using OpenCL and FPGAs

FPGA Can be Implemented Using Advanced Encryption Standard Algorithm

This paper mainly focused on implementation of AES encryption and decryption standard AES-128. All the transformations of both Encryption and Decryption are simulated using an iterativedesign approach in order to minimize the hardware consumption. This method can make it avery low-complex architecture, especially in saving the hardware resource in implementing theAES InverseSub Bytes module and...

Hardware Implementation of Dynamic S-BOX to Use in AES Cryptosystem

One of the major cipher symmetric algorithms is AES. Its main feature is to use S-BOX step, which is the only non-linear part of this standard possessing fixed structure. During the previous studies, it was shown that AES standard security was increased by changing the design concepts of S-BOX and production of dynamic S-BOX. In this paper, a change of AES standard security is studied by produc...

FPGA vs GPU Performance Comparison on the Implementation of FIR Filters

FIR filters find place in digital signal processing applications that require stopping a frequency band while passing another band or removing noise. Due to the complex structure and parallelism property of FIR filters, dedicated reconfigurable hardware are preferred for implementation rather than CPUs. Recently, GPGPU emerged as an effective technique for solving computation-intensive problems...

The Presentation of an Ideal Safe SMS based model in mobile Electronic commerce using Encryption hybrid algorithms AES and ECC

Mobile commerce is whatever electronic transfer or transaction via a mobile modem through a mobile net in which the true value or advance payment is done for goods, services or information. A mobile payment system should be beneficial for all related persons. For a payment system to be a Successful system, End-user, seller, exporter and operators should see a additional value in it. End-user ...